| 零件編號 | Description | Key Feature | Status | Datasheet |
| SSD2805 | MIPI Master Bridge with 2-lane | Transmission Rates up to 700Mbps over 2 Data Lanes, Supports 16/18/24-bpp Display for Both MCU & RGB interfaces | Mass Production | REV 1.1 |
| SSD2825 | MIPI Master Bridge with 4-lane | Transmission Rates up to 2.4Gbps over 4 Data Lanes, Supports 16/18/24-bpp Display for Both MCU & RGB interfaces | Mass Production | REV 0.4 |
Solomon Systech MIPI Master Bridge Chips SSD2805/SSD2825 support high-speed, low-power displays in application-rich mobile devices.
SSD2825 is able to support display resolutions of up to WXGA (1280x800) at video speed, whereas SSD2805 supports up to WVGA (480x854).Both can support a main panel and a sub panel simultaneously. Furthermore, it adopts the physical layer of low voltage differential signaling as defined by MIPI specifications.
The SSD2805/SSD2825 is versatile enough to be interface with most baseband processors, application processors or co-processors now deploying in mobile products. The SSD2805/SSD2825 is able to operate in both High-Speed (HS) and Low-Power (LP) modes for data transmission to provide optimum power consumption, and will consume ultra-low power in the idle state. It contains an on-chip PLL for clock generation.
Features
—Support MIPI specification with maximum 4-lane
—Supports MCU interface of 8/16 bits (6800 and 8080), RGB interface
—(16/18/24 bits) and SPI interface (8-bit 3-wire, 8-bit 4-wire, or 24-bit 3-wire)
—Support 16/18/24 bit-per-pixel
—Support dual panel update
—Support High-Speed (HS) and Low-Power (LP) Mode for data transmission
—Support ultra-low Power Mode in idle state
—Support both Command Mode and Video Mode in MIPI DSI standard
—Support bi-directional data transfer (forward link in High-Speed and Low-Power —Modes and reverse link in Low-Power Mode)
—On-chip PLL: reference input clock frequency: 10-20 MHz
—Power supply: 1.2V +/- 10% for Internal Circuit: 3.3V/1.8V +/- 10% for I/Os