|Part Number||Description||Key Feature||Status||Datasheet|
|SSD2805||MIPI Master Bridge with 2-lane||Transmission Rates up to 700Mbps over 2 Data Lanes, Supports 16/18/24-bpp Display for Both MCU & RGB interfaces||Mass Production||Send Request|
|SSD2825||MIPI Master Bridge with 4-lane||Transmission Rates up to 2.4Gbps over 4 Data Lanes, Supports 16/18/24-bpp Display for Both MCU & RGB interfaces||Mass Production||Send Request|
|SSD2828||MIPI Master Bridge with 4-lane||Transmission rate up to 4.0Gbps over 4 Data lanes. Support 16/18/24 bpp. Display for both MCU & RGB interface||Mass Production||Send Request|
|SSD2848||4-lane MIPI in, 4-lane MIPI out bridge chip||Transmission rate support up to 4 x 1.5Gbps lanes. display up to 1920*1200||Mass Production||Send Request|
|SSD2858||4-lane MIPI in, 8-lane MIPI out bridge chip||Rx support up to 4 x 1.5Gbps lanes, Tx support up to 8 x 1.0Gbps lanes, display up to 2560*1600||Mass Production||Send Request|
Solomon Systech MIPI Master Bridge Chips SSD2805/SSD2825/SSD2828 support high-speed, low-power displays in application-rich mobile devices.
SSD2828 is able to support display resolution of up to WUXGA (1920x1200), while SSD2825 and SSD2805 are able to support display resolutions of up to WXGA (1280x800) and WVGA (480x854) respectively. All ICs adopt the physical layer of low voltage differential signaling as defined by MIPI specifications.
SSD2805/SSD2825/SSD2828 are versatile enough to be interface with most baseband processors, application processors or co-processors now deploying in mobile products. SSD2805/SSD2825/SSD2828 are able to operate in both High-Speed (HS) and Low-Power (LP) modes for data transmission to provide optimum power consumption, and will consume ultra-low power in the idle state. It contains an on-chip PLL for clock generation.
—Support MIPI specification with maximum 4-lane
—Supports MCU interface of 8/16 bits (6800 and 8080), RGB interface
—(16/18/24 bits) and SPI interface (8-bit 3-wire, 8-bit 4-wire, or 24-bit 3-wire)
—Support 16/18/24 bit-per-pixel
—Support dual panel update
—Support High-Speed (HS) and Low-Power (LP) Mode for data transmission
—Support ultra-low Power Mode in idle state
—Support both Command Mode and Video Mode in MIPI DSI standard
—Support bi-directional data transfer (forward link in High-Speed and Low-Power —Modes and reverse link in Low-Power Mode)
—On-chip PLL: reference input clock frequency: 10-20 MHz
—Power supply: 1.2V +/- 10% for Internal Circuit: 3.3V/1.8V +/- 10% for I/Os